- Pre-Layout Analysis
-
Pre-Layout Overview 0 hr 2 min
-
Transmission Line Libraries 0 hr 2 min
-
Substrate Editor 0 hr 2 min
-
Controlled Impedance Line Designer 0 hr 12 min
-
Via Designer 0 hr 18 min
-
Build Channel Models 0 hr 2 min
-
SnP Component 0 hr 4 min
-
Lab 1: Controlled Impedance Line Designer and Via Designer 2 hr 40 min
-
Knowledge Check 0 hr 5 min
- Channel Simulation
-
Channel Simulator 0 hr 8 min
-
IBIS-AMI Modeling for High-Speed SERDES 0 hr 12 min
-
Channel Simulation Palette 0 hr 8 min
-
Channel Simulation Results 0 hr 10 min
-
Additional tools in ADS for SI simulation 0 hr 12 min
-
Memory Designer 0 hr 28 min
-
Chiplets 0 hr 4 min
-
Lab 2: Design a channel and channel simulation 3 hr 30 min
-
Knowledge Check 0 hr 5 min
- Summary and Next Step
-
Claim your certificate
Pre-Layout Analysis and Channel Simulation
You will learn how to deal with pre-layout phase for SI/HSD designers in ADS, how to use Channel simulator with IBIS-AMI models
+ Learning Objectives
Pre-Layout Analysis
- Controlled Impedance Line Designer, Via Designer, Transmission Line Libraries
- Lab 1: Design a differential pair on different layer with CILD & design differential vias with via designer tool.
Channel Simulation
- Channel Simulation using IBIS-AMI Model, Mix and Match Simulations, NRZ and PAM-X Signal
- Lab 2: Build a channel, channel simulation of backdrilled vias, comparison of backdrilled vias with non backdrilled vias (through vias), optimize the channel performance, channel simulation with IBIS-AMI model, mix and match simulation, PAM4 signal channel simulation.
+ Content Types
- Video Lessons
- Hands-on Labs
- Knowledge Check
+ Who should take this course?
- For SI/PI/HSD engineers
+ Prerequisites