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Controlled Impedance Line Designer, Via Designer, Transmission Line Libraries
Learn to model complex interconnects—transmission lines and vias—and combine them into cohesive schematics for signal integrity and EM simulation
Curriculum3 hr 47 min
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Content
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Pre-Layout Design Flow 0 hr 2 min
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Transmission Line Libraries 0 hr 2 min
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Controlled Impedance Line Designer 0 hr 14 min
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Build Channel Models 0 hr 2 min
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Lab 1: CILD and Via Designer 3 hr 0 min
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Knowledge Check 0 hr 5 min
Curriculum3 hr 47 min
-
Content
-
Pre-Layout Design Flow 0 hr 2 min
-
Transmission Line Libraries 0 hr 2 min
-
Controlled Impedance Line Designer 0 hr 14 min
-
-
Build Channel Models 0 hr 2 min
-
-
Lab 1: CILD and Via Designer 3 hr 0 min
-
Knowledge Check 0 hr 5 min
