Get Started with High-Speed Digital
For SI/PI/HSD engineers
Creating and Simulating Schematics
Component palettes, simulation controllers, data display
FREE
1 hr 19 min
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Lab: S-Parameter Analysis
This lab covers schematic creation, parameterization, tuning, and data display. You will build a transmission line using lumped elements, transition it to a distributed model, and analyze its group delay.
FREE
1 hr 30 min
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Lab: Transient Analysis
You will execute transient simulations to analyze signal propagation and compare TEM vs. non-TEM transmission lines. You will also quantify S-bend interconnect degradation and interpret eye diagrams to assess signal integrity.
FREE
1 hr 30 min
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Connectivity Design and Layout Basics
Working with Design Kits, Path/Trace Routing and Editing, Snap Modes, Placement and Editing, Technology Files
FREE
0 hr 35 min
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Lab: Intro to ADS Architecture
This lab introduces technology files (including layers and units), component libraries, and basic layout manipulation.
FREE
1 hr 30 min
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Lab: Create Custom Layers
You will modify the existing default layers to save time with pre-built colors and patterns, or design a custom technology completely from scratch.
FREE
1 hr 0 min
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Lab: Component Interconnect Creation and Editing
This lab shows how to create interconnects, and how to insert and edit shapes.
FREE
1 hr 30 min
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Pre-Layout Analysis
Controlled impedance line designer, Via designer
FREE
0 hr 47 min
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Lab: Controlled Impedance Line Designer
Design a 100 Ohm top-layer microstrip differential pair and an internal embedded stripline differential pair.
FREE
1 hr 30 min
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Lab: Via Designer
Use Via Designer to model backdrilled and standard vias
FREE
1 hr 30 min
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Channel Simulation
Model, simulate, and characterize a complete end-to-end channel—from transmitter to receiver.
FREE
1 hr 1 min
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Lab: Via Stub Effects on Eye Diagram
You will build a channel model, simulate a backdrilled PCB, and compare backdrilled versus non-backdrilled vias
FREE
1 hr 30 min
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Lab: Optimize the Channel Performance
You will use the Optimizer to maximize the eye opening by tuning the Layer 3 differential line impedance and the transmitter de-emphasis.
FREE
1 hr 0 min
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Lab: Channel Simulation with IBIS-AMI Model
You will run a channel simulation using IBIS-AMI models.
FREE
1 hr 0 min
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Lab: Mix and Match Simulation
Simulate a hybrid channel (Generic TX + IBIS-AMI RX, or IBIS-AMI TX + Generic RX)
FREE
1 hr 0 min
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Lab: PAM4 Signal Channel Simulation
Build a 56 Gbps PAM4 IBIS-AMI channel using your earlier differential line design
FREE
1 hr 0 min
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Signal Integrity Analysis
SIPro EM simulation, using SIPro simulation results
FREE
1 hr 12 min
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Lab: Working with ODB++ Layouts
In this lab, you will learn to manage imported PCB layouts. Tasks include importing an ODB++ layout with its associated technology file, investigating the layout architecture, and utilizing the Net-based connectivity mode to check layout interconnects
FREE
1 hr 30 min
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Lab: Learn SIPro/PIPro Flow
Master the SIPro/PIPro interface, visibility controls, analysis setup, net/component filtering, and port creation to extract interconnect S-parameters from complex PCBs.
FREE
2 hr 0 min
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Lab: Power-Aware Signal Integrity Analysis
Set up the power-aware SI analysis for PCB: define ports for the DQ5 line and power nets, assign component models, execute the simulation, and generate the final subcircuit.
FREE
1 hr 45 min
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Lab: Comparing Ideal and Power-Aware Channel Interconnects
Evaluate the eye diagram under two conditions: first, with ideal VRM, FPGA, and memory IC connections; second, using a power-aware channel model to capture power plane impedance, data line SI, and coupling effects (SSN/ground bounce).
FREE
0 hr 45 min
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DC and AC IR Drop, Power Plane Resonances
Identify critical IR drop regions and optimize the PDN by minimizing impedance
FREE
0 hr 46 min
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Lab: Setup a PIPro DC Analysis
The first Power Integrity analysis you will perform is DC IR drop on a PC3 UDIMM PCB. You will set up the models for the VRM and Sinks
FREE
1 hr 0 min
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Lab: VRM to IC Voltage Drop Analysis
In this lab, you will analyze the voltage drop from the VRM to the memory ICs to ensure the DC voltage at the chip input is sufficiently large for stable operation. You will run a PIPro DC analysis, inspect the results, and generate a test bench and subcircuit.
FREE
1 hr 0 min
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Lab: PDN AC Impedance Analysis
Convert a DC IR drop analysis into a PIPro AC PDN impedance analysis, map component models to analyze chip-to-VRM impedance profiles with decaps, and perform decap optimization.
FREE
1 hr 30 min
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Thermal/Electro-Thermal Analysis
Heat dissipation in PCB’s, temperature profiles
FREE
0 hr 26 min
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Lab: Thermal Analysis
The analysis focuses on two key ICs—the Main Multimedia Processor and the Phoenix Audio IC—on the Panda Board, an 8-layer, 11cm x 10 cm development platform
FREE
1 hr 30 min
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Lab: Electrothermal Analysis
Convert a standard DC simulation into an electrothermal analysis using VRMs and sinks. Analyze TRET-derived thermal resistance and dissipation factors, then compare the IR drop results in the Sink tab across both simulation types.
FREE
0 hr 45 min
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