There was an issue with saving this content. Please try again.
There was an issue with removing this item from your saved content. Please try again.
Lab: Comparing Ideal and Power-Aware Channel Interconnects
Course 21 of 28 in Get Started with High-Speed Digital
Evaluate the eye diagram under two conditions: first, with ideal VRM, FPGA, and memory IC connections; second, using a power-aware channel model to capture power plane impedance, data line SI, and coupling effects (SSN/ground bounce).
