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Signal Integrity Analysis
SIPro EM simulation, using SIPro simulation results
Curriculum1 hr 12 min
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Importing ODB++
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Importing ODB++ 0 hr 5 min
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Validate Substrate Stackup 0 hr 2 min
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Navigator window 0 hr 2 min
-
Knowledge Check 0 hr 5 min
-
SIPro
-
SIPro/PIPro Capabilities 0 hr 8 min
-
SIPro/PIPro Flow 0 hr 14 min
-
SIPro/PIPro Window 0 hr 2 min
-
Setup SI Analysis 0 hr 10 min
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Run SIPro Simulation 0 hr 2 min
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Inspect Results 0 hr 4 min
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Generate Schematic Model 0 hr 2 min
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Transient/Convolution Simulation 0 hr 6 min
-
Knowledge Check 0 hr 10 min
Curriculum1 hr 12 min
-
Importing ODB++
-
Importing ODB++ 0 hr 5 min
-
Validate Substrate Stackup 0 hr 2 min
-
Navigator window 0 hr 2 min
-
Knowledge Check 0 hr 5 min
-
SIPro
-
SIPro/PIPro Capabilities 0 hr 8 min
-
SIPro/PIPro Flow 0 hr 14 min
-
SIPro/PIPro Window 0 hr 2 min
-
Setup SI Analysis 0 hr 10 min
-
Run SIPro Simulation 0 hr 2 min
-
Inspect Results 0 hr 4 min
-
Generate Schematic Model 0 hr 2 min
-
Transient/Convolution Simulation 0 hr 6 min
-
Knowledge Check 0 hr 10 min
