Using Verilog-A Models

How to use Verilog-A models in IC-CAP

rate limit

Code not recognized.

Curriculum0 hr 23 min

  • Content
  • Prepare Folders and Files 0 hr 5 min
  • Set up link to ADS Simulator 0 hr 2 min
  • Simulate with Diode Model 0 hr 5 min
  • Extract and Export Model 0 hr 8 min
  • Checkpoint 0 hr 3 min

Curriculum0 hr 23 min

  • Content
  • Prepare Folders and Files 0 hr 5 min
  • Set up link to ADS Simulator 0 hr 2 min
  • Simulate with Diode Model 0 hr 5 min
  • Extract and Export Model 0 hr 8 min
  • Checkpoint 0 hr 3 min

Ready to Get Started?

CONTACT SALES