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Post-Layout Overview 0 hr 2 min
- Importing ODB++
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Importing Layouts 0 hr 12 min
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Connectivity in ADS Layout 0 hr 2 min
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Navigator window 0 hr 2 min
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Lab 1: Working with ODB++ layouts 1 hr 30 min
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Knowledge Check 0 hr 5 min
- Learn SIPro/PIPro Flow
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SIPro & PIPro Simulation Capabilities 0 hr 12 min
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SIPro / PIPro Analysis Flow 0 hr 18 min
- Power-Aware SI Analysis
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Power-Aware SI Analysis 0 hr 2 min
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SIPro EM Simulation 0 hr 12 min
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Using SIPro Simulation Results 0 hr 2 min
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Single-Ended vs Differential Component Models 0 hr 2 min
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Power-Aware Transient/Convolution Simulations 0 hr 8 min
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Lab 2: Learn SIPro/PIPro Flow 2 hr 0 min
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Lab 3: Power-Aware SI Analysis 2 hr 0 min
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Knowledge Check 0 hr 10 min
- PIPro DC IR Drop
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PIPro Analysis Types 0 hr 2 min
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PIPro DC IR Drop Analysis 0 hr 18 min
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Lab 4: PDN DC IR Drop 1 hr 30 min
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Knowledge Check 0 hr 5 min
- PDN AC Impedance
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PDN AC Impedance Analysis 0 hr 16 min
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Lab 5: PDN AC Impedance 1 hr 30 min
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Knowledge Check 0 hr 5 min
- Electrothermal (ET) Analysis
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Electro-Thermal Modeling 0 hr 8 min
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Thermal Conductivities 0 hr 4 min
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Thermal Resistance Extraction Tool (TRET) 0 hr 6 min
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Thermal Source Models 0 hr 4 min
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Thermal Simulator Options 0 hr 2 min
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Electrothermal vs Thermal Analysis 0 hr 2 min
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Thermal Results 0 hr 2 min
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Lab 6: Thermal/Electrothermal analysis 1 hr 40 min
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Knowledge Check 0 hr 5 min
- Summary and Next Step
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Claim your certificate
SIPro / PIPro / Electrothermal
You will learn how to setup simulations with SIPro and PIPro (Post-Layout Analysis), how to tune the HSD design to simulate the behavior of real-world PCB imported into ADS
+ Learning Objectives
Importing ODB++
- Import / export, connectivity modes, Net names
- Lab 1: Import ODB++ layout with technology, investigate the imported layout, Net-based connectivity mode
SIPro
- Learn SIPro and PIPro flow
- Lab 2: Inspect SIPro/PIPro window elements, setup an SI analysis of a signal interconnect, run SIPro simulation of an interconnect and inspect results, Net identification and layer visibility.
- Power-aware signal integrity analysis
- Lab 3: You will simulate eye diagram for a FPGA memory line that goes from IC socket to a DDR4 chip where both FPGA and DDR4 chips are modelled using IBIS files. Setup power-aware SIPro analysis of the interconnection and associated PDN. Study the difference between ideal connections between VRM, FPGA and memory IC and power-aware interconnect model where PDN fluctuations due to data line dynamic behaviour are included.
PIPro
- PIPro DC IR drop analysis
- Lab 4: Analyse the voltage drop from VRM to memory IC to make sure the DC voltage seen at the chip inputs is sufficiently large for stable operation.
- PDN AC Impedance analysis
- Lab 5: Convert the DC IP drop analysis to a PIPro AC Impedance analysis of the PDN. Associate component simulation models to the imported instances to be able to look at the impedance profiles from the chip to the VRM considering the decoupling capacitors. Performing decap optimizations.
Electrothermal (ET) Analysis
- Heat dissipation in PCB’s, temperature profiles.
- Lab 6: Setup a thermal analysis of a PCB and then ET analysis.
+ Content Types
- Video Lessons
- Hands-on Labs
- Knowledge Check
+ Who should take this course?
- For SI/PI/HSD engineers
+ Prerequisites